IFS, Structural Design Engineer
Job DescriptionIntel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs. With the first "Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient, and sustainable source of supply.
This job opportunity in IFS will be part of the Customer Solutions Engineering (CSE) group which is responsible for the portions of the system foundry that brings the "best of Intel" technologies to IFS customers, differentiating and accelerating their solutions from architecture to post-silicon validation.
In this role you will:
Perform physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Conduct all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Achieving final convergence.
Analyzes results and make recommendations to fix violations for current and future product architecture.
Possess expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
Optimize and converge design to improve product-level parameters such as power, frequency, and area.
Participate in the development and improvement of physical design methodologies and flow automation
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates
Bachelor or Master of Science degree in Electrical Engineering or Computer Engineering
2+ years of related industry experience
Possesses overall experience in structural and physical design, and limited expertise and experience in a specific limited area: Ex. physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
Preferred and Additional Qualifications:
Post graduate degree Electrical Engineering, Computer Engineering, Computer Science, or in a related field of study
Demonstrate experience and hands-on practical knowledge with standard-cell based VLSI design methodology and relevant industry standard EDA tools.
Demonstrate strong analytical and problem solving skills through relevant experiences with ASIC/SOC design convergence.
Excellent communication and leadership skills are a strong plus.
Demonstrate experience in scripting with Unix shell, Perl and TCL.
Self-driven with ability to prioritize work and accomplish tasks quickly with good problem solving skills.
Must be detail oriented with solid written and verbal communication for expressing technical ideas and initiatives
Comfortable task switching and managing multiple tasks at the same time
Good understanding of digital design, circuits, layout with a thorough understanding of CMOS processes