Component Debug Engineering Manager
Pulau Pinang, 马来西亚
职位 ID JR0268612
职位类别 Silicon Hardware Engineering
工作模式 Hybrid
经验级别 Experienced
工时类型 全职
Job Description
Evaluates and resolves component engineering design and physical design issues. Ensures products have necessary design for debug features to enable deep silicon isolation capabilities. Utilizes system setups, testing equipment, automated systems, and lab probe/FIB/prep tools to isolate microscopic silicon circuits while under test. Performs fault isolation to root cause silicon failures, isolate defect modes, and engages with crossfunctional teams such as test and validation engineers, circuit designers, wafer fabrication process engineers, and high volume manufacturing for efficient and accelerated failure analysis. Partners to resolve any quality issues, sharing ownership of failure analysis, temporary mitigation options, and permanent remedies. Provides inputs on investigation areas for failure analysis or design process improvement and ensure performance to specifications. Develops new debug technologies, methodologies, and tools to advance the state of the art for silicon debug.Qualifications
Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences. Minimum Qualifications: - Must have minimum Bachelor degree in Electrical Engineering or Computer Engineering. - Minimum 7 years experience in a pre-silicon logic or circuit design role, or a post-silicon functional or electrical validation role. - Minimum 1 year experience in at least one programming or scripting language such as PERL and Python. - Strong analytical ability, problem solving and communication skills. - Strong leadership traits in people and program management. Preferred Qualifications: - ASIC/VLSI design skills - Logic design skills and experience in Verilog or VHDL coding - Knowledge of JTAG/TAP functionality - Experience in Testing ATE/VLSI - Coursework in relevant areas of programming, digital design, and computer architecture desirableInside this Business Group
The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change...Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Maggie 前沿安全研究员
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