Signal integrity intern

Job Description

DCAI China engineering and architecture team is the driving force to accelerate datacenter business growth in China. Our charter is to deliver Xeon based platform designs, provide best in class support for datacenter customers in China, as well as creating innovative and customized platforms and solutions that best serve this vibrant market and eco-system in China. This end-to-end capability will enable us winning this market by translating marketing insight into required technologies that empower digital transformation, operating as a world class engineering team, co-innovating with eco-system partners and collaborate closely with all global teams across Intel. Your technical expertise can be fully utilized, your great potential can be fully unleashed in this highly inclusive, energized and nimble engineering team who are at the front of driving leading-edge technology transition for datacenter market. In this position, you will be responsible for the signal integrity design for Intel next generation server board and system product based on Intel Processor and chipsets. Your responsibilities will include but not limit to: � Performs comprehensive simulations and validations to generate Intel design guidelines to guide system level signal integrity design including silicon, package, socket and boards. � Performs SI simulations and timing analysis, and correlating simulations with system measurements. � Provides SI simulation models and collaterals for Intel customers. � Interacts cross function teams like silicon circuit design, package design, board design, board fabricators, etc, for ensuring the proper implementation of high-speed interfaces such as UPI, DDR, PCIe, SATA/SAS, and system SI for clocks, power, etc. � Defines system/board architectures, review the PCB layout and approve Reference Board (RP) tape out.

Qualifications

Minimum qualifications: � Must have an MS (with minimum 1+ years SI experiences) or PhD in Electrical Engineering or Electrical and Computer Engineering � Proved experiences on silicon, package and board level signal integrity. � Board-level system architecture, I/O structures topologies � Package, Printed Circuit Board (PCB) design and layout process and methodology � Experience with signal integrity modeling tools, including 3D EM modeling (Ansys HFSS) and simulation (Agilent ADS or similar) software � Experience with signal integrity analysis tools (ex: HSPICE, Sigrity tools, etc) � Lab hands on experiences on TDR, VNA, BERTscope, digital scopes, logic analyzers, and multi-meters

Inside this Business Group

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

CN, GD, Shenzhen; CN, BJ, Beijing

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will require an on-site presence.* Job posting details (such as work model, location or time type) are subject to change.