CPLD Engineer

Job Description

About Intel AI:

Intel AI is at the forefront of developing cutting-edge AI processors, designed from the ground up to excel in both training deep neural networks and powering high-performance inference in production environments. We are a dynamic and innovative team dedicated to pushing the boundaries of AI technology.

Position Overview: We are seeking a talented and motivated CPLD Design Engineer with system management background (Powe/reset sequencing, interrupt HW handling, I2C/SPI/JTAG muxing, ect) to join our team as a CPLD designer engineer and  system management lead. As a key member of the hardware engineering department, you will be responsible for designing and developing complex systems using Lattice CPLDs (Complex Programmable Logic Devices). This role involves designing digital logic, writing and optimizing HDL code, IP implementation in code including CPU soft IP, security handling, programming flow implementation and working closely with cross-functional teams to integrate your designs into larger systems.

Key Responsibilities:

• System management: Design architecture and implementation plan for board system  mangment
• CPLD Design & Development: Design, implement, and verify digital logic systems using Lattice CPLDs.
• HDL Programming: Write, simulate, and optimize VHDL or Verilog code for efficient hardware implementations.
• System Integration: Work with hardware engineers to integrate CPLD-based solutions into larger embedded systems or electronic products.
• Design Verification: Perform simulations, timing analysis, and functional verification to ensure the correctness and robustness of your designs.
• Optimization: Focus on optimizing designs for performance and resource usage within the constraints of Lattice CPLDs.
• Collaboration: Collaborate with firmware validation and production teams and customers to ensure seamless integration and overall system functionality.
• Documentation: Create and maintain design specifications, documentation, and test plans for all projects.
• Continuous Learning: Stay updated with new Lattice CPLD technologies, design tools, and industry best practices to improve the quality of your work and the overall design process.

Qualifications

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree is a plus)
• Experience:
  • Minimum of 2-5 years of experience in digital design, with a focus on CPLDs or FPGAs.
  • Proficient in HDL languages (VHDL or Verilog).
  • C for CPLD (RISC-V code)
  • Python
  • Hands-on experience with Lattice development tools (e.g., Lattice Diamond, Radiant, or Synplify).
  • Experience in designing and testing embedded systems.
• Skills:
  • Strong understanding of digital logic design, state machines, and timing analysis.
  • Capable of strong system wide view understanding
  • Experience with simulation and debugging tools (e.g., ModelSim, Questa, etc.).
  • Knowledge of PCB design, signal integrity, and hardware interfacing.
  • Familiarity with FPGA/CPLD architectures and toolchain optimizations.
• Soft Skills:
  • Excellent problem-solving and analytical skills.
  • Strong communication skills to interact with various engineering teams.
  • Ability to work independently and as part of a collaborative team.

Primary Location:

• Caesarea  

Inside this Business Group

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.