Analog Circuit Design Engineer

Job Description

Designs, develops, and builds analog circuits in advanced process nodes for analog and mixedsignal IPs. Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models. Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results. Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals. Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues. Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications

Bachelor's degree in Electronics Engineering, Electrical Engineering, or related field with 2+ years’ relevant experience OR Master’s degree in Electronics Engineering, Electrical Engineering or related filed with 6 months’ relevant experience in the following areas:

• Design and analysis of analog circuits such as OPAMP, ADC, LDO, PLL, Temperature Sensors, IO, BG, oscillators.

• Good understanding of analog circuit layout techniques.

• Strong understanding of semiconductor device physics and behavior, transistors, and basic circuit components.

• Experience with circuit design environment & related tools such as HSpice, LTSpice, Cadence, Synopsys.

• Experience using scripting languages such as Python or Perl.

• Strong analytical and problem-solving skills.

• Excellent verbal and written communication skills, with the ability to present technical information clearly and concisely.

Preferred Qualifications

• Master's degree in Electronics Engineering, Electrical Engineering, or related field with 3+ years in Analog Circuit Design.

• Good understanding of interaction between digital and analog blocks at a system level.

• Familiarity with Verilog / System Verilog / VHDL hardware coding languages.

• Familiarity analyzing, validating and debugging analog circuits in a post-silicon environment.

• Experience with design for manufacturability (DFM) and design for testability (DFT) considerations.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.