SoC Physical Silicon Chip Lead

Job Description

Our Design team is looking for a Physical Design Engineer to contribute to high performance/low power designs using best methods in synthesis, placement, and route. In addition to Physical Design Engineering, you will also run our back-end validation and verification tools.

Your responsibility will include but not limited to:

- Block level and/or SoC floor-planning.
- Voltage area and power grid implementation.
- Implementation of APR flows using Synopsys Fusion Compiler tool.
- Static Timing Analysis using Synopsys PrimeTime.
- Power Analysis and power optimization using RedHawk and PTPX.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

Candidate must possess a BS degree with 8+ years of experience or MS degree with 6+ years of experience or PhD degree with 4+ years of experience in Electrical/Computer Engineering, Computer Science, or related STEM field.

In addition, 8+ years of experience in:

- Synopsys or Cadence design (RTL to GDS) tools.
- Synopsys-Primetime and PTPX for both STA timing and power analysis.
- Coding both UPF and timing constraints files at both partition and SoC levels.
- Perl, TCL/Tk programming.
- Floor-planning activities including trade-offs in Macro placements, Power Grid definition, and integration requirements.
- Perform DRC and LVS layout verification activities.

Preferred Qualifications:

- Experience with RTL/Logic design Verilog.
- Highly organized with the ability to prioritize and multi-task effectively.
- Experience with TFM (Tools, Flows, Methodology) Development.
- Effective interpersonal communication skills including written verbal and presentation.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, OR, Hillsboro; US, TX, Austin; US, AZ, Phoenix; US, CA, San Jose

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.